~ruther/verilog-riscv-semestral-project

ref: 7ad5176683d16ac95ec356d2fe57bc9c753d698b verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
7ad51766 — Rutherther fix: remove duplicit instruction and pc in cpu 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd