~ruther/verilog-riscv-semestral-project (6da6eb9e4ee2ac5f96d5bed40c4c46d57a64c79f): .gitignore

~ruther/verilog-riscv-semestral-project

ref: 6da6eb9e4ee2ac5f96d5bed40c4c46d57a64c79f verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes

6da6eb9e — Rutherther docs: better document the stage code, organize it better 1 year, 4 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/