~ruther/verilog-riscv-semestral-project

ref: 66d141635b81de276634d3d9f97fe46c0ffb2f32 verilog-riscv-semestral-project/tests/comp_list.lst -rwxr-xr-x 332 bytes
66d14163 — Rutherther feat: move jumping to execute stage 1 year, 4 months ago
                                                                                
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src/cpu_types.sv
src/instruction_decoder.sv
src/control_unit.sv
src/alu.sv
src/register_file.sv
src/program_counter.sv

src/forwarder.sv

src/stages/fetch.sv
src/stages/decode.sv
src/stages/execute.sv
src/stages/memory_access.sv
src/stages/writeback.sv

src/ram.sv
src/cpu.sv
src/file_program_memory.sv

testbench/tb_cpu_program.sv
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