~ruther/verilog-riscv-semestral-project

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66d14163 — Rutherther feat: move jumping to execute stage 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/