~ruther/verilog-riscv-semestral-project

ref: 586cf7122913dbe1faece5e92b9da4bfc0d36403 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes
586cf712 — Rutherther chore: clearer naming 1 year, 3 months ago
                                                                                
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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git
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