~ruther/verilog-riscv-semestral-project (586cf7122913dbe1faece5e92b9da4bfc0d36403): .gitignore

~ruther/verilog-riscv-semestral-project

ref: 586cf7122913dbe1faece5e92b9da4bfc0d36403 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes

586cf712 — Rutherther chore: clearer naming 1 year, 3 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/