~ruther/verilog-riscv-semestral-project

ref: 4dcef0207792f0c7e7ba6f1f9fe95432c4a872c3 verilog-riscv-semestral-project/src/stages/fetch.sv -rw-r--r-- 336 bytes
4dcef020 — Rutherther docs: document pipeline a bit 1 year, 4 months ago 
                                                                                
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import cpu_types::*;

module fetch(
  input        clk,
  input [31:0] pc,
  input [31:0] mem_instruction,
  input        jump,

  output       stage_status_t stage_out
);
  assign stage_out.instruction.instruction = mem_instruction;
  assign stage_out.valid = !jump;
  assign stage_out.pc = pc;
  assign stage_out.ready = 1;
endmodule
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