~ruther/verilog-riscv-semestral-project

ref: 4dcef0207792f0c7e7ba6f1f9fe95432c4a872c3 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes
4dcef020 — Rutherther docs: document pipeline a bit 1 year, 10 months ago 
                                                                                
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void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}