~ruther/verilog-riscv-semestral-project

ref: 4dcef0207792f0c7e7ba6f1f9fe95432c4a872c3 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes
4dcef020 — Rutherther docs: document pipeline a bit 1 year, 5 months ago
                                                                                
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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git
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