~ruther/verilog-riscv-semestral-project (34b74f067674498d19ea3797dfaa3330ce1514f0): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: 34b74f067674498d19ea3797dfaa3330ce1514f0 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

34b74f06 — Rutherther tests: add python test environment for custom tests 1 year, 6 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}