~ruther/verilog-riscv-semestral-project

ref: 34b74f067674498d19ea3797dfaa3330ce1514f0 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 96 bytes
34b74f06 — Rutherther tests: add python test environment for custom tests 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat