~ruther/verilog-riscv-semestral-project (32388b786d96e16d5264fe541d217ba5ca6b7084): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: 32388b786d96e16d5264fe541d217ba5ca6b7084 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

32388b78 — Rutherther feat: add support for loading and saving ram from disk 1 year, 7 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}