~ruther/verilog-riscv-semestral-project (308a146292087449ecb82e4b7935f789ab21c64b): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 308a146292087449ecb82e4b7935f789ab21c64b verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

308a1462 — Rutherther tests: add register dump, printing 1 year, 5 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git