~ruther/verilog-riscv-semestral-project

ref: 2f09f768fe5d2888738e473802f708ad6fa8f794 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
2f09f768 — Rutherther fix: make immediates sign extended 2 years ago 
                                                                                
1
2
3
4
5
6
7
8

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd