~ruther/verilog-riscv-semestral-project (280332ea3bcdd58544d3b1606eedd54fda0f1611): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: 280332ea3bcdd58544d3b1606eedd54fda0f1611 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

280332ea — Rutherther fix: make Makefile work with memory load, write files 1 year, 5 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}