~ruther/verilog-riscv-semestral-project (280332ea3bcdd58544d3b1606eedd54fda0f1611): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 280332ea3bcdd58544d3b1606eedd54fda0f1611 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

280332ea — Rutherther fix: make Makefile work with memory load, write files 2 years ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git