~ruther/verilog-riscv-semestral-project

ref: 24eccbe0e5c0dabfc068a993b5167510756a4e22 verilog-riscv-semestral-project/.envrc -rwxr-xr-x 10 bytes
24eccbe0 — Rutherther refactor: parametrize register file 2 years ago 
                                                                                
1

use flake