~ruther/verilog-riscv-semestral-project (1d7c9233527974f1bfd8db7e0027d5871911b997): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 1d7c9233527974f1bfd8db7e0027d5871911b997 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

1d7c9233 — Rutherther chore: add python cache to gitignore 1 year, 6 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git