ditigal.xyz
git
Log in
—
Register
~ruther
/
verilog-riscv-semestral-project
summary
tree
log
refs
ref:
11422de00c50854a650da69469f3646f4e2f500b
verilog-riscv-semestral-project
/
programs
/start.S
-rwxr-xr-x
95 bytes
View
Log
View raw
Permalink
11422de0
— Rutherther feat: store c results in memory addr 0
1 year, 5 months ago
1
2
3
4
5
6
7
8
9
.global
_start
.text
_start:
addi
sp
,
x0
,
124
call
main
_loop:
ebreak
j
_loop
Do not follow this link