~ruther/verilog-riscv-semestral-project

ref: 11422de00c50854a650da69469f3646f4e2f500b verilog-riscv-semestral-project/programs/link.ld -rwxr-xr-x 291 bytes
11422de0 — Rutherther feat: store c results in memory addr 0 1 year, 5 months ago 
                                                                                
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MEMORY
{
    ram : ORIGIN = 0x00000000, LENGTH = 1K - 1
}

SECTIONS
{
	.text = 0x0;
    .bss : {
        __bss_start = .;
        *(.bss)
        *(COMMON)
        __bss_end = .;
    } > ram
    .stack : {
        __stack_start = .;
        *(.stack)
        __stack_end = .;
    } > ram
}
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