~ruther/verilog-riscv-semestral-project

ref: 0d5d1a1fc04a21df2c7cf81ce969e9c02c125901 verilog-riscv-semestral-project/programs/add.c -rwxr-xr-x 171 bytes
0d5d1a1f — Rutherther fix: sign extend only when misaligned access 1 year, 4 months ago 
                                                                                
1
2
3
4
5
6
7
8
9
10
11
12
13
14

int add(int a, int b)
{
    return a + b;
}

void main()
{
    int a = 20;
    int b = 30;
    int c = add(a, b);

    int* result_address = 0;
    *result_address = c;
}
Do not follow this link