~ruther/verilog-riscv-semestral-project

ref: 0d5d1a1fc04a21df2c7cf81ce969e9c02c125901 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes
0d5d1a1f — Rutherther fix: sign extend only when misaligned access 1 year, 11 months ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/