~ruther/verilog-riscv-semestral-project

ref: fb02ebb264bda787ca3441964dfa1fe6e69ca6ef verilog-riscv-semestral-project/tests/official/official_tests.py -rwxr-xr-x 1.4 KiB 
tests: add register dump, printing

feat: add support for official tests
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