~ruther/verilog-riscv-semestral-project: tests/official/Makefile fb02ebb264bda787ca3441964dfa1fe6e69ca6ef

~ruther/verilog-riscv-semestral-project

ref: fb02ebb264bda787ca3441964dfa1fe6e69ca6ef verilog-riscv-semestral-project/tests/official/Makefile -rwxr-xr-x 618 bytes

18eeb2c5 — Rutherther 2 years ago

tests: compile only once, copy proram, memory files to correct locations

51842d38 — Rutherther 2 years ago

feat: add support for official tests