~ruther/verilog-riscv-semestral-project

ref: e5d2c0c5de0541507c602b1d9a5cff2a0cc88494 verilog-riscv-semestral-project/tests/official d---------
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
18eeb2c5 — Rutherther 2 years ago
tests: compile only once, copy proram, memory files to correct locations
51842d38 — Rutherther 2 years ago
feat: add support for official tests