~ruther/verilog-riscv-semestral-project: tests/official/env/p/riscv_test.h df876b38b787b7f1e9120775311a0b1a17e2758b

~ruther/verilog-riscv-semestral-project

ref: df876b38b787b7f1e9120775311a0b1a17e2758b verilog-riscv-semestral-project/tests/official/env/p/riscv_test.h -rwxr-xr-x 8.2 KiB

308a1462 — Rutherther 2 years ago

tests: add register dump, printing

51842d38 — Rutherther 2 years ago

feat: add support for official tests