~ruther/verilog-riscv-semestral-project

ref: df876b38b787b7f1e9120775311a0b1a17e2758b verilog-riscv-semestral-project/tests/custom/custom_tests.py -rwxr-xr-x 1.8 KiB 
tests: add register dump, printing

feat: add support for official tests
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