~ruther/verilog-riscv-semestral-project

ref: af6386a7cb0eb3b58cd754956dca300d416cbcde verilog-riscv-semestral-project/tests/official d---------
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
18eeb2c5 — Rutherther 2 years ago
tests: compile only once, copy proram, memory files to correct locations
51842d38 — Rutherther 2 years ago
feat: add support for official tests