~ruther/verilog-riscv-semestral-project: testbench/tb_ram.sv af6386a7cb0eb3b58cd754956dca300d416cbcde

~ruther/verilog-riscv-semestral-project

ref: af6386a7cb0eb3b58cd754956dca300d416cbcde verilog-riscv-semestral-project/testbench/tb_ram.sv -rwxr-xr-x 818 bytes

db85fb35 — Rutherther 2 years ago

tests: fix ram and control_unit tests to match newest architecture

0a9a14b7 — Rutherther 2 years ago

test: add ram test