~ruther/verilog-riscv-semestral-project: testbench/tb_ram.sv aeab403896e168bc0c44a65883d46bb96689b7fb

~ruther/verilog-riscv-semestral-project

ref: aeab403896e168bc0c44a65883d46bb96689b7fb verilog-riscv-semestral-project/testbench/tb_ram.sv -rwxr-xr-x 818 bytes

db85fb35 — Rutherther 1 year, 6 months ago

tests: fix ram and control_unit tests to match newest architecture

0a9a14b7 — Rutherther 1 year, 7 months ago

test: add ram test