~ruther/verilog-riscv-semestral-project: testbench/tb_cpu_simple.sv acf0f7243e7b45dc7db8e51c5c7ae659f7ef2bb3

~ruther/verilog-riscv-semestral-project

ref: acf0f7243e7b45dc7db8e51c5c7ae659f7ef2bb3 verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rwxr-xr-x 2.4 KiB

acf0f724 — Rutherther 2 years ago

feat: implement sb, sh, lb, lh support via masking

773f4b99 — Rutherther 2 years ago

test: add simple cpu test