~ruther/verilog-riscv-semestral-project: testbench acf0f7243e7b45dc7db8e51c5c7ae659f7ef2bb3

~ruther/verilog-riscv-semestral-project

ref: acf0f7243e7b45dc7db8e51c5c7ae659f7ef2bb3 verilog-riscv-semestral-project/testbench d---------

acf0f724 — Rutherther 1 year, 7 months ago

feat: implement sb, sh, lb, lh support via masking

773f4b99 — Rutherther 1 year, 7 months ago

test: add simple cpu test

2929a779 — Rutherther 1 year, 7 months ago

test: add basic testbenches