~ruther/verilog-riscv-semestral-project: tests/official/env/p/riscv_test.h a079c57bf9f1ab9cca6147599107bdd01e034121

~ruther/verilog-riscv-semestral-project

ref: a079c57bf9f1ab9cca6147599107bdd01e034121 verilog-riscv-semestral-project/tests/official/env/p/riscv_test.h -rwxr-xr-x 8.2 KiB

308a1462 — Rutherther 2 years ago

tests: add register dump, printing

51842d38 — Rutherther 2 years ago

feat: add support for official tests