~ruther/verilog-riscv-semestral-project: tests/test_types.py 94c41794fa83c9d5c25d362920dc2ee4b5d48288

~ruther/verilog-riscv-semestral-project

ref: 94c41794fa83c9d5c25d362920dc2ee4b5d48288 verilog-riscv-semestral-project/tests/test_types.py -rwxr-xr-x 928 bytes

308a1462 — Rutherther 2 years ago

tests: add register dump, printing

51842d38 — Rutherther 2 years ago

feat: add support for official tests