~ruther/verilog-riscv-semestral-project: tests/official/Makefile 914e69e6c0df1f4e3f33718891c838e42fe535b1

~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/tests/official/Makefile -rwxr-xr-x 618 bytes

18eeb2c5 — Rutherther 1 year, 5 months ago

tests: compile only once, copy proram, memory files to correct locations

51842d38 — Rutherther 1 year, 5 months ago

feat: add support for official tests