~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/tests/official d--------- 
tests: add register dump, printing

tests: compile only once, copy proram, memory files to correct locations

feat: add support for official tests
Do not follow this link