~ruther/verilog-riscv-semestral-project: testbench/tb_ram.sv 914e69e6c0df1f4e3f33718891c838e42fe535b1

~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/testbench/tb_ram.sv -rwxr-xr-x 818 bytes

db85fb35 — Rutherther 1 year, 4 months ago

tests: fix ram and control_unit tests to match newest architecture

0a9a14b7 — Rutherther 1 year, 5 months ago

test: add ram test