~ruther/verilog-riscv-semestral-project: src/cpu.sv 8f631f51a777c2aa139b677706608f2189c091a3

~ruther/verilog-riscv-semestral-project

ref: 8f631f51a777c2aa139b677706608f2189c091a3 verilog-riscv-semestral-project/src/cpu.sv -rwxr-xr-x 3.0 KiB

8f631f51 — Rutherther 1 year, 5 months ago

refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.

82d9e44f — Rutherther 1 year, 5 months ago

feat: add cpu top level entity