~ruther/verilog-riscv-semestral-project: src/control_unit.sv 8f631f51a777c2aa139b677706608f2189c091a3

~ruther/verilog-riscv-semestral-project

ref: 8f631f51a777c2aa139b677706608f2189c091a3 verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 2.5 KiB

52b05e5d — Rutherther 1 year, 5 months ago

feat: add control_unit wrapper over instruction_decoder