~ruther/verilog-riscv-semestral-project

ref: 82d9e44f3229f6554dade8f51988d313a1df02dc verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 2.5 KiB
52b05e5d — Rutherther 2 years ago 
feat: add control_unit wrapper over instruction_decoder