~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/tests/official/env d---------
79c7be5c — Rutherther 2 years ago main 
chore: remove unnecessary executable flags

Closes #4.
308a1462 — Rutherther 2 years ago 
tests: add register dump, printing
51842d38 — Rutherther 2 years ago 
feat: add support for official tests