~ruther/verilog-riscv-semestral-project

ref: 681756b70c4accd8c4caec6e97d8275a6359e5f9 verilog-riscv-semestral-project/tests/official/official_tests.py -rwxr-xr-x 1.4 KiB 
tests: add register dump, printing

feat: add support for official tests
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