~ruther/verilog-riscv-semestral-project: tests/official/Makefile 681756b70c4accd8c4caec6e97d8275a6359e5f9

~ruther/verilog-riscv-semestral-project

ref: 681756b70c4accd8c4caec6e97d8275a6359e5f9 verilog-riscv-semestral-project/tests/official/Makefile -rwxr-xr-x 618 bytes

18eeb2c5 — Rutherther 1 year, 8 months ago

tests: compile only once, copy proram, memory files to correct locations

51842d38 — Rutherther 1 year, 8 months ago

feat: add support for official tests