~ruther/verilog-riscv-semestral-project: testbench/tb_ram.sv 66d141635b81de276634d3d9f97fe46c0ffb2f32

~ruther/verilog-riscv-semestral-project

ref: 66d141635b81de276634d3d9f97fe46c0ffb2f32 verilog-riscv-semestral-project/testbench/tb_ram.sv -rwxr-xr-x 818 bytes

db85fb35 — Rutherther 2 years ago

tests: fix ram and control_unit tests to match newest architecture

0a9a14b7 — Rutherther 2 years ago

test: add ram test