~ruther/verilog-riscv-semestral-project

ref: 60517957c80d84b8a6514adc0dd416634e9a88e6 verilog-riscv-semestral-project/tests/test_types.py -rwxr-xr-x 928 bytes
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
51842d38 — Rutherther 2 years ago
feat: add support for official tests