~ruther/verilog-riscv-semestral-project: testbench/tb_ram.sv 5fe030988a21d47dd13af35a9b8697b2181cb6b7

~ruther/verilog-riscv-semestral-project

ref: 5fe030988a21d47dd13af35a9b8697b2181cb6b7 verilog-riscv-semestral-project/testbench/tb_ram.sv -rwxr-xr-x 632 bytes

0a9a14b7 — Rutherther 2 years ago

test: add ram test