~ruther/verilog-riscv-semestral-project: tests/official/Makefile 586cf7122913dbe1faece5e92b9da4bfc0d36403

~ruther/verilog-riscv-semestral-project

ref: 586cf7122913dbe1faece5e92b9da4bfc0d36403 verilog-riscv-semestral-project/tests/official/Makefile -rwxr-xr-x 618 bytes

18eeb2c5 — Rutherther 2 years ago

tests: compile only once, copy proram, memory files to correct locations

51842d38 — Rutherther 2 years ago

feat: add support for official tests