~ruther/verilog-riscv-semestral-project

ref: 4dcef0207792f0c7e7ba6f1f9fe95432c4a872c3 verilog-riscv-semestral-project/tests/official/official_tests.py -rwxr-xr-x 1.4 KiB
308a1462 — Rutherther 2 years ago 
tests: add register dump, printing
51842d38 — Rutherther 2 years ago 
feat: add support for official tests