~ruther/verilog-riscv-semestral-project

ref: 4dcef0207792f0c7e7ba6f1f9fe95432c4a872c3 verilog-riscv-semestral-project/tests/official/env/p/riscv_test.h -rwxr-xr-x 8.2 KiB 
tests: add register dump, printing

feat: add support for official tests
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