~ruther/verilog-riscv-semestral-project

ref: 4dcef0207792f0c7e7ba6f1f9fe95432c4a872c3 verilog-riscv-semestral-project/tests/official d---------
308a1462 — Rutherther 2 years ago
tests: add register dump, printing
18eeb2c5 — Rutherther 2 years ago
tests: compile only once, copy proram, memory files to correct locations
51842d38 — Rutherther 2 years ago
feat: add support for official tests